1. Field of the Invention
The invention relates to the field of integrated circuit, metal-oxide-semiconductor (MOS) transistors and in particular to the fabrication of electrical contacts to substrate regions.
2. Prior Art
There has been much discussion about using materials having low dielectric constants (e.g., less than 4) and materials having low density for interlayer dielectrics (ILDs) in integrated circuits. By lowering the capacitance between conductors separated by the ILDs, power reduction and speed increases are both possible.
As will be seen with the present invention, a low k material or a low density dielectric can be used to provide additional benefits in connection with the fabrication of contacts to the substrate.
In the cross sectional elevation view of FIG. 1, the silicon substrate 10 includes source/drain regions 11 and 12 formed in the substrate 10 which define a channel. A polysilicon gate 13 is insulated from this channel by a insulative layer such as a silicon dioxide layer 14. FIG. 1 also illustrates an isolation region 15, specifically a silicon dioxide filled trench which is commonly used to separate active regions of field-effect transistors. An overlying insulative layer 17 is typically deposited over the structure of FIG. 1 and, in subsequent processing, an opening 16 is etched through the layer 17 to enable a metal contact to contact, for instance, the region 12. Numerous steps and structures often used such as spacers for aligning lightly doped source/drain regions and protective oxides used during the fabrication to protect for example the gate 13, are not illustrated.
As can be seen in FIG. 1, the region 12 is relatively elongated. This is done so that when the contact opening 16 is etched through the layer 17, it lands on the region 12. This is important since if the contact opening were to expose the gate 13, when the contact is formed the gate 13 and region 12 would be connected "shorting" the transistor. Note that the opening 16 is not self-aligned in that the mask used to define the opening (and the other such openings in the layer 17) must be aligned by moving the mask itself relative to the substrate. The mask must be aligned so that the opening is exactly over the targeted regions and not, for instance, over the gate 13 or the region 15. Consequently, the region 12 is elongated to provide compensation for masking alignment tolerances. This increases the amount of substrate area required for the transistor and hence, reduces circuit density and increases junction capacitance.
FIG. 2 shows another prior art technique for providing contact to the substrate 20. In the cross-sectional elevation view of FIG. 2, the source/drain regions 21 and 22 define a channel which is insulated from the gate 23 by the insulative layer. In connection with the formation of the gate 23 a relatively thick silicon nitride cap 29 is formed over the gate 23. Additionally, a silicon nitride layer 28 is deposited over the substrate and as can be seen, protects the sides of the gate 23. A insulative layer 27 such as silicon dioxide layer, is deposited over the layer 28.
The opening 26 is etched to contact the region 22. Unlike the opening 16 of FIG. 1, opening 26 need not be precisely aligned over region 22. That is, the opening 26 can be "unlanded" and can, in fact, in part expose the relatively thick silicon nitride cap over the gate 23 or the thinner nitride layer 28 deposited over the isolation region 25.
In etching the opening 26, a first etchant is used which more readily etches the material of layer 27 than silicon nitride. Consequently, the silicon nitride acts as an etchant stop, allowing the layer 27 to be etched without the gate 23 becoming exposed even though the opening is not entirely over the region 22. Then a second etchant is used, for instance in an anisotropic etching step, to etch the silicon nitride, thereby exposing the region 22. The relatively thicker cap 29 over the gate 23 prevents the gate from being exposed. Moreover, the anisotropic etching spares most of layer 28 that is vertically aligned on the side of gate 23. When a contact is formed in the opening 26, it only makes a conductive path to the region 22 because the gate is protected by the silicon nitride. Note that as shown in FIG. 2, the region 22 need not be large enough for the opening land solely on the targeted region. Accordingly, region 22 may be smaller than region 62 of FIG. 1, thereby permitting fabrication of denser circuits.
The unlanded contact shown in FIG. 2 is difficult to reliably achieve. It is difficult to obtain high enough etchant selectivity between the layer 27 and the layer 28. Typical selectivity of 5-to-1 is achievable and this is not high enough for reliable manufacturing. Moreover, the process of FIG. 2, when compared to the processing of FIG. 1, requires additional steps such as depositing the etchant stop layer 28.